From: Stefan Biereigel <stefan@biereigel.de>
Date: Mon, 27 May 2019 16:01:44 +0000 (+0200)
Subject: remove leftovers from ast data structures
X-Git-Tag: yosys-0.9~102^2~2^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd12f2ddcfbdbfbf147afc2c90ddc54ec1f74485;p=yosys.git

remove leftovers from ast data structures
---

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 963152588..44b8863f9 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -51,7 +51,6 @@ namespace AST_INTERNAL {
 	std::map<std::string, AstNode*> current_scope;
 	const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
 	RTLIL::SigSpec ignoreThisSignalsInInitial;
-	std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
 	AstNode *current_always, *current_top_block, *current_block, *current_block_child;
 	AstModule *current_module;
 	bool current_always_clocked;
@@ -943,8 +942,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 		log("--- END OF AST DUMP ---\n");
 	}
 
-	wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>();
-
 	if (!defer)
 	{
 		bool blackbox_module = flag_lib;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index c2a7744c4..6c19dc7e6 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -327,7 +327,6 @@ namespace AST_INTERNAL
 	extern std::map<std::string, AST::AstNode*> current_scope;
 	extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
 	extern RTLIL::SigSpec ignoreThisSignalsInInitial;
-	extern std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map;
 	extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;
 	extern AST::AstModule *current_module;
 	extern bool current_always_clocked;