From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 24 Aug 2016 13:30:08 +0000 (+0200)
Subject: Added SV "restrict" keyword
X-Git-Tag: yosys-0.7~107
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd18235f30221ea2a5d51ab8b1d2639f51f1e99d;p=yosys.git

Added SV "restrict" keyword
---

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index aafdbbf03..0c974d392 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -177,7 +177,8 @@ YOSYS_NAMESPACE_END
 
 "assert"   { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
 "assume"   { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
-"predict"   { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
+"restrict" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
+"predict"  { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
 "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
 "logic"    { SV_KEYWORD(TOK_REG); }
 "bit"      { SV_KEYWORD(TOK_REG); }