From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 28 Jul 2018 04:43:10 +0000 (+0100)
Subject: split out slow memory map to separate file
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd1a8807d6b58e97d4c2b8baf893dabf6439a425;p=pinmux.git

split out slow memory map to separate file
---

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index de2aaf9..636197e 100644
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -7,14 +7,10 @@ package slow_peripherals;
 	import AXI4_Types::*;
 	import Semi_FIFOF::*;
 	import AXI4Lite_AXI4_Bridge::*;
+	import slow_memory_map::*;
 	`include "instance_defines.bsv"
-    /* ==== define the AXI Addresses ==== */
-{2}
     /* ==== define the number of slow peripheral irqs ==== */
 {11}
-    /*====== AXI4 Lite slave declarations =======*/
-
-{3}
 	/*===========================*/
 	/*=== package imports ===*/
 	import Clocks::*;
@@ -61,27 +57,6 @@ package slow_peripherals;
 	endinterface
 	/*================================*/
 
-	function SlowTuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
-                     fn_address_mapping (Bit#(`ADDR) addr);
-        `ifdef CLINT
-            if(addr>=`ClintBase && addr<=`ClintEnd)
-                return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
-            else
-        `endif
-        `ifdef PLIC
-            if(addr>=`PLICBase && addr<=`PLICEnd)
-                return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
-            else
-        `endif
-        `ifdef AXIEXP
-            if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
-                return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
-            else
-        `endif
-{4}
-        return tuple2(False,?);
-	endfunction
-
 	(*synthesize*)
 	module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
                                Clock uart_clock, Reset uart_reset
diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 12fdecc..6cf1f2d 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -86,6 +86,8 @@ def pinmuxgen(pth=None, verify=True):
     idef = os.path.join(bp, 'instance_defines.bsv')
     slow = os.path.join(bp, 'slow_peripherals.bsv')
     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
+    slowmf = os.path.join(bp, 'slow_memory_map.bsv')
+    slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
     soc = os.path.join(bp, 'socgen.bsv')
     soct = os.path.join(cwd, 'soc_template.bsv')
 
@@ -94,14 +96,16 @@ def pinmuxgen(pth=None, verify=True):
     write_bvp(bvp, p, ifaces)
     write_bus(bus, p, ifaces)
     write_instances(idef, p, ifaces)
-    write_slow(slow, slowt, p, ifaces, iocells)
+    write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
     write_soc(soc, soct, p, ifaces, iocells)
 
 
-def write_slow(slow, slowt, p, ifaces, iocells):
+def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
     """ write out the slow_peripherals.bsv file.
         joins all the peripherals together into one AXI Lite interface
     """
+    with open(slowmt) as bsv_file:
+        slowmt = bsv_file.read()
     with open(slowt) as bsv_file:
         slowt = bsv_file.read()
     imports = ifaces.slowimport()
@@ -125,6 +129,8 @@ def write_slow(slow, slowt, p, ifaces, iocells):
                                     pincon, inst, mkplic,
                                     numsloirqs, ifacedef,
                                     inst2))
+    with open(slowmf, "w") as bsv_file:
+        bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
 
 
 def write_soc(soc, soct, p, ifaces, iocells):