From: Tim Ansell <me@mith.ro>
Date: Wed, 3 Oct 2018 23:38:32 +0000 (-0700)
Subject: xilinx: Adding missing inout IO port to IOBUF
X-Git-Tag: yosys-0.9~116^2~21
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd261795ba6942c4d249925fe008db34a8dd46cf;p=yosys.git

xilinx: Adding missing inout IO port to IOBUF
---

diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index a2dd01ad5..f5abf3ae0 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -2225,6 +2225,7 @@ module IOBUF (...);
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
     output O;
+    inout IO;
     input I, T;
 endmodule