From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Nov 2018 09:24:12 +0000 (+0000)
Subject: fix fsgn elwidth
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd29490db202474b3943b676f27710b54f13125f;p=riscv-isa-sim.git

fix fsgn elwidth
---

diff --git a/id_regs.py b/id_regs.py
index a1fdf67..035ae43 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -100,13 +100,16 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
                 dest_flen = 64
             elif split[1].startswith('q'):
                 dest_flen = 128
-        if "f128(" in f:
+        if "f128(" in f or \
+                insn.startswith('fsgn') and insn.endswith('q'):
             src_flen = 128
             dest_flen = 128
-        elif "f64(" in f or insn == 'fsd':
+        elif "f64(" in f or insn == 'fsd' or \
+                insn.startswith('fsgn') and insn.endswith('d'):
             src_flen = 64
             dest_flen = 64
-        elif "f32(" in f or insn == 'fsw':
+        elif "f32(" in f or insn == 'fsw' or \
+                insn.startswith('fsgn') and insn.endswith('s'):
             src_flen = 32
             dest_flen = 32
         for pattern in patterns: