From: Dmitry Selyutin Date: Sun, 28 May 2023 22:04:57 +0000 (+0300) Subject: ppc: support dsrd instruction X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd2f743e5db41e0f07fb92760d17131d1518f22a;p=binutils-gdb.git ppc: support dsrd instruction --- diff --git a/gas/testsuite/gas/ppc/dsrd.d b/gas/testsuite/gas/ppc/dsrd.d new file mode 100644 index 00000000000..a44381813aa --- /dev/null +++ b/gas/testsuite/gas/ppc/dsrd.d @@ -0,0 +1,16 @@ +#as: -mlibresoc +#objdump: -dr -Mlibresoc + +.*: file format .* + + +Disassembly of section \.text: +0+ <\.text>: +.*:\s+(13 e0 00 36|36 00 e0 13)\s+dsrd\s+r31,r0,r0,r0 +.*:\s+(10 1f 00 36|36 00 1f 10)\s+dsrd\s+r0,r31,r0,r0 +.*:\s+(10 00 f8 36|36 f8 00 10)\s+dsrd\s+r0,r0,r31,r0 +.*:\s+(10 00 07 f6|f6 07 00 10)\s+dsrd\s+r0,r0,r0,r31 +.*:\s+(13 e0 00 37|37 00 e0 13)\s+dsrd.\s+r31,r0,r0,r0 +.*:\s+(10 1f 00 37|37 00 1f 10)\s+dsrd.\s+r0,r31,r0,r0 +.*:\s+(10 00 f8 37|37 f8 00 10)\s+dsrd.\s+r0,r0,r31,r0 +.*:\s+(10 00 07 f7|f7 07 00 10)\s+dsrd.\s+r0,r0,r0,r31 diff --git a/gas/testsuite/gas/ppc/dsrd.s b/gas/testsuite/gas/ppc/dsrd.s new file mode 100644 index 00000000000..96faf9a469e --- /dev/null +++ b/gas/testsuite/gas/ppc/dsrd.s @@ -0,0 +1,8 @@ +dsrd 31,0,0,0 +dsrd 0,31,0,0 +dsrd 0,0,31,0 +dsrd 0,0,0,31 +dsrd. 31,0,0,0 +dsrd. 0,31,0,0 +dsrd. 0,0,31,0 +dsrd. 0,0,0,31 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 6f41bb48b35..cc4c755df1e 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -172,3 +172,4 @@ run_dump_test "maddedu" run_dump_test "divmod2du" run_dump_test "sadd" run_dump_test "dsld" +run_dump_test "dsrd" diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 7f4486a2ae4..96037806129 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -5216,6 +5216,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, {"dsld", VA2(4,26,0), VA2_MASK, SFFS, PPCVLE, {RT, RA, RB, RC}}, {"dsld.", VA2(4,26,1), VA2_MASK, SFFS, PPCVLE, {RT, RA, RB, RC}}, +{"dsrd", VA2(4,27,0), VA2_MASK, SFFS, PPCVLE, {RT, RA, RB, RC}}, +{"dsrd.", VA2(4,27,1), VA2_MASK, SFFS, PPCVLE, {RT, RA, RB, RC}}, {"vextduhvrx", VX (4, 27), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, {"vextduwvlx", VX (4, 28), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}},