From: Rick Altherr <kc8apf@kc8apf.net>
Date: Sun, 31 Jan 2016 03:25:35 +0000 (-0800)
Subject: rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)
X-Git-Tag: yosys-0.6~30^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd3e1095b0c77e3a58feff259b7612e9701f6ce4;p=yosys.git

rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7878eaae7..91b737151 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2659,8 +2659,35 @@ void RTLIL::SigSpec::remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other
 
 void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other)
 {
-	pool<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_pool();
-	remove2(pattern_bits, other);
+	if (other)
+		cover("kernel.rtlil.sigspec.remove_other");
+	else
+		cover("kernel.rtlil.sigspec.remove");
+
+	unpack();
+	if (other != NULL) {
+		log_assert(width_ == other->width_);
+		other->unpack();
+	}
+
+	for (int i = GetSize(bits_) - 1; i >= 0; i--) {
+		if (bits_[i].wire == NULL) continue;
+
+		for (auto &pattern_chunk : pattern.chunks()) {
+			if (bits_[i].wire == pattern_chunk.wire &&
+				bits_[i].offset >= pattern_chunk.offset &&
+				bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
+				bits_.erase(bits_.begin() + i);
+				width_--;
+				if (other != NULL) {
+					other->bits_.erase(other->bits_.begin() + i);
+					other->width_--;
+				}
+			}
+		}
+	}
+
+	check();
 }
 
 void RTLIL::SigSpec::remove(const pool<RTLIL::SigBit> &pattern)