From: Luke Kenneth Casson Leighton Date: Fri, 13 May 2022 18:03:45 +0000 (+0100) Subject: add 3-way bridge phy X-Git-Tag: opf_rfc_ls005_v1~2255 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd3e6d15eb6bdd85875196fa15edc091b76dac99;p=libreriscv.git add 3-way bridge phy --- diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index d3825489f..a4a11cae6 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -808,10 +808,23 @@ execute the exact same ISA (or a subset of it). If however the concept of Hybrid PE-Memory Processing were to become a JEDEC Standard, which would increase adoption and reduce cost, a bit more thought is required here because ARM or Intel or MIPS might not necessarily -be happy that a Processing Element has to execute Power ISA binaries. +be happy that a Processing Element (PE) has to execute Power ISA binaries. At least the Power ISA is much richer, more powerful, still RISC, and is an Open Standard, as discussed in a earlier sections. +A reasonable compromise in this regard however is illustrated with +the following diagram: a 3-way Bridge PHY that allows for full +direct interaction between DRAM ICs, PEs, and one or more main CPUs +(* a variant of the Northbridge and/or IBM POWER10 OMI-to-DDR5 PHY concept*). +It is also the ideal location for a "Management Core" +There is also no reason why this type of arrangement should not be deployed +in Multi-Chip-Module (aka "Chiplet") form, giving all the advantages of +the performance boost that goes with smaller line-drivers. + +Draft Image (placeholder): + + + # Transparently-Distributed Vector Processing It is very strange to the author to be describing what amounts to a diff --git a/openpower/sv/bridge_phy.jpg b/openpower/sv/bridge_phy.jpg new file mode 100644 index 000000000..9616bee6c Binary files /dev/null and b/openpower/sv/bridge_phy.jpg differ