From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Mar 2022 21:20:15 +0000 (+0000)
Subject: sort out hyperram ports down to test class
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd44c0fc57e955f263760892203575be70202fc4;p=lambdasoc.git

sort out hyperram ports down to test class
---

diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py
index 446e495..02e3d5f 100644
--- a/lambdasoc/periph/hyperram.py
+++ b/lambdasoc/periph/hyperram.py
@@ -94,6 +94,16 @@ class HyperRAMPads:
         self.cs_n = Signal()
         self.dq   = Record([("oe", 1), ("o", dw),     ("i", dw)])
         self.rwds = Record([("oe", 1), ("o", dw//8),  ("i", dw//8)])
+        self.dq.o.name = "dq_o"
+        self.dq.i.name = "dq_i"
+        self.dq.oe.name = "dq_oe"
+        self.rwds.o.name = "rwds_o"
+        self.rwds.i.name = "rwds_i"
+        self.rwds.oe.name = "rwds_oe"
+
+    def ports(self):
+        return [self.ck, self.cs, self.dq.o, self.dq.i, self.dq.oe,
+                self.rwds.o, self.rwds.oe]
 
 
 class HyperRAMPHY(Elaboratable):
@@ -114,8 +124,8 @@ class HyperRAMPHY(Elaboratable):
         return m
 
     def ports(self):
-        return [self.ck, self.cs, self.dq_o, self.dq_i, self.dq_oe,
-                self.rwds_o, self.rwds_oe]
+        return self.pads.ports()
+
 
 # HyperRAM --------------------------------------------------------------------