From: Matthew Malcomson <matthew.malcomson@arm.com>
Date: Thu, 9 May 2019 09:29:21 +0000 (+0100)
Subject: [binutils][aarch64] New sve_size_013 iclass.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd50a87ae29f163e7d254729a902a5e51fcccbbc;p=binutils-gdb.git

[binutils][aarch64] New sve_size_013 iclass.

Add sve_size_013 instruction class

This new iclass handles instructions such as pmullb whose size specifier
can only be encoded as 0, 1, or 3.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_013 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_013 iclass decode.
---

diff --git a/include/ChangeLog b/include/ChangeLog
index 28e00bfcec8..600e753f060 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
 	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 0df8bddfd1c..9cc73cad223 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -596,6 +596,7 @@ enum aarch64_insn_class
   sve_size_sd,
   sve_size_bh,
   sve_size_sd2,
+  sve_size_013,
   testbranch,
   cryptosm3,
   cryptosm4,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d0f28ced24d..a8051cd5002 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+	sve_size_013 iclass encode.
+	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+	sve_size_013 iclass decode.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
 	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 674eba5e9d3..0ec27b24928 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1613,6 +1613,7 @@ do_special_encoding (struct aarch64_inst *inst)
 static void
 aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
 {
+  int variant = 0;
   switch (inst->opcode->iclass)
     {
     case sve_cpy:
@@ -1669,6 +1670,13 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
 		    aarch64_get_variant (inst) + 1, 0);
       break;
 
+    case sve_size_013:
+      variant = aarch64_get_variant (inst);
+      if (variant == 2)
+	  variant = 3;
+      insert_field (FLD_size, &inst->value, variant, 0);
+      break;
+
     default:
       break;
     }
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index bfc47b4c1b8..1a727a4ba84 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2822,6 +2822,16 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
       variant = i - 1;
       break;
 
+    case sve_size_013:
+      i = extract_field (FLD_size, inst->value, 0);
+      if (i == 2)
+	return FALSE;
+      if (i == 3)
+	variant = 2;
+      else
+	variant = i;
+      break;
+
     default:
       /* No mapping between instruction class and qualifiers.  */
       return TRUE;