From: Florent Kermarrec Date: Sat, 25 May 2019 07:24:25 +0000 (+0200) Subject: README: update RISC-V toolchain X-Git-Tag: 24jan2021_ls180~1200 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd543b290ca149f97e598add442e4067c630fd6b;p=litex.git README: update RISC-V toolchain --- diff --git a/README b/README index 88357cb0..be15f513 100644 --- a/README +++ b/README @@ -99,9 +99,9 @@ FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_10 ./litex_setup.py update 2. Install a RISC-V toolchain: - wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz - tar -xvf riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz - export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin/ + wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz + tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz + export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/ 3. Build the target of your board...: Go to boards/targets and execute the target you want to build