From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 14 Aug 2020 23:03:49 +0000 (+0100)
Subject: remove latchregister, use sync to capture compunit results
X-Git-Tag: semi_working_ecp5~337
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd5bce6ab706a6d40e0fd0795b00a5d5372e30e6;p=soc.git

remove latchregister, use sync to capture compunit results
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index fe1b93c0..c4dcfd15 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -270,11 +270,14 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
                 # bye-bye abstract interface design..
                 fname = find_ok(data_r.fields)
                 if fname:
-                    ok = data_r[fname]
+                    ok = getattr(lro, fname)
             else:
                 data_r = Signal.like(lro, name=name, reset_less=True)
             wrok.append(ok & self.busy_o)
-            latchregister(m, lro, data_r, alu_pulsem, name + "_l")
+            with m.If(alu_pulse):
+                m.d.sync += data_r.eq(lro)
+            with m.Elif(self.issue_i):
+                m.d.sync += data_r.eq(0)
             drl.append(data_r)
 
         # ok, above we collated anything with an "ok" on the output side