From: colepoirier <colepoirier@gmail.com>
Date: Mon, 8 Jun 2020 01:17:43 +0000 (-0700)
Subject: Fix spelling
X-Git-Tag: div_pipeline~480
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd5c4eb369c6cbfed065b4a9981b5d4c31e43c60;p=soc.git

Fix spelling
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index bd1611f8..c9f5d143 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -84,7 +84,7 @@ class TrapMainStage(PipeModBase):
 
         # addr to begin from on return
         comb += srr0_o.data.eq(return_addr)
-        comb += srro_o.ok.eq(1) # spelling
+        comb += srr0_o.ok.eq(1)
 
         # TODO: MSR (into srr1)