From: lkcl <lkcl@web>
Date: Sat, 23 Oct 2021 18:01:24 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3548
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd6906d5e19a62f85339652caf3248dbf9e1318d;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn
index 59f44212f..48cb5a425 100644
--- a/3d_gpu/architecture/dynamic_simd/slice.mdwn
+++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn
@@ -183,6 +183,24 @@ specified by "x", at each elwid:
     0b01 x x x x  x AaA9A8 x x x x  x A2A1A0
     0b10 x AeAdAc x AaA9A8 x A6A5A4 x A2A1A0
 
+The presence of "x" unused portions actually requires some additional
+partition points:
+
+    elwid |      | |      | |      | |
+    0b00 x x x x  x x x x  x x x x  x A2A1A0
+    0b01 x x x x  x AaA9A8 x x x x  x A2A1A0
+    0b10 x AeAdAc x AaA9A8 x A6A5A4 x A2A1A0
+
+Now let us take a signal, b, of 2-bit, and the same number of
+PartitionPoints,
+and perform an add operation:
+
+
+    elwid |    | |    | |    | |
+    0b00 x x x  x x x  x x x  x B1B0
+    0b01 x x x  x A9A8 x x x  x A1A0
+    0b10 x AdAc x A9A8 x A5A4 x A1A0
+
 Illustrating the case where a Sliced (fixed element width) SimdSignal
 is added to one which has variable-length elements that take up the
 entirety of the partition (overall fixed width):