From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Mar 2015 16:12:35 +0000 (+0100)
Subject: soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx... 
X-Git-Tag: 24jan2021_ls180~2494
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd6c04b24faf1e0eb72e28b5a8b0c10d0e1a6693;p=litex.git

soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx
---

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index df4322eb..e9fbca15 100644
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -50,7 +50,15 @@ class SDRAMSoC(SoC):
 				self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
 
 			if self.with_l2:
-				self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
+				# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
+				# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
+				# Remove this workaround when fixed by Xilinx.
+				from mibuild.xilinx.vivado import XilinxVivadoPlatform
+				if isinstance(self.platform, XilinxVivadoPlatform):
+					from migen.fhdl.simplify import FullMemoryWE
+					self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
+				else:
+					self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
 				lasmic = self.sdram.controller.lasmic
 				sdram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
 				self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)