From: lkcl <lkcl@web>
Date: Tue, 15 Dec 2020 18:21:06 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1312
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd71e4083cfada5a56c542d6159d535ef51360bf;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 7b50d715a..64dda389e 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -26,6 +26,13 @@ Side-effects:
 
 * mtcrweird when RA=0 is a means to set or clear arbitrary CR bits from immediates
 
+(Twin) Predication interactions:
+
+* INT twin predication with zeroing is a way to copy an integer into CRs without necessarily needing the INT register (RA).  if it is, it is effectively ANDed (or negate-and-ANDed) with the INT Predicate
+* CR twin predication with zeroing is likewise a way to interact with the incoming integer
+
+this gets particularly powerful if data-dependent predication is also enabled.
+
 # Instruction form and pseudocode
 
     | 0-5 | 6-10  | 11 | 12-15 | 16-18 | 19-20 | 21-30 | 31 |