From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 12 Oct 2019 17:20:50 +0000 (+0200)
Subject: cpu/lm32: add missing buses
X-Git-Tag: 24jan2021_ls180~911
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd8213b988c5e67de55cd98dec0eff0485d72f7e;p=litex.git

cpu/lm32: add missing buses
---

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index f41345bb..522a0377 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -40,6 +40,7 @@ class LM32(CPU):
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()
         self.interrupt = Signal(32)
+        self.buses     = [i, d]
 
         # # #