From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 01:21:08 +0000 (-0700)
Subject: Reject if (* init *) present
X-Git-Tag: working-ls180~1039^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd8a640989d0819266d2678304951de2a247405d;p=yosys.git

Reject if (* init *) present
---

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 9330dd09b..6b6d2b56f 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -333,6 +333,9 @@ code
 			reject;
 		if (c.wire->get_bool_attribute(\keep))
 			reject;
+		Const init = c.wire->attributes.at(\init, State::Sx);
+		if (!init.is_fully_undef() && !init.is_fully_zero())
+			reject;
 	}
 endcode
 
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index e256f7d7e..0a345e88d 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -355,6 +355,9 @@ code
 			reject;
 		if (c.wire->get_bool_attribute(\keep))
 			reject;
+		Const init = c.wire->attributes.at(\init, State::Sx);
+		if (!init.is_fully_undef() && !init.is_fully_zero())
+			reject;
 	}
 endcode