From: Segher Boessenkool Date: Tue, 4 Jun 2019 23:32:21 +0000 (+0200) Subject: rs6000: Simplify for VSX_TI X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd9346a157c48d3fc5a059ca763ecb74178abeb8;p=gcc.git rs6000: Simplify for VSX_TI When used in VSX_TI, is always just "wa". * config/rs6000/vsx.md: Replace all that are used with VSX_TI with just "wa". From-SVN: r271933 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f7eff36e5fc..213132f83f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-06-04 Segher Boessenkool + + * config/rs6000/vsx.md: Replace all that are used with VSX_TI + with just "wa". + 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "ww"): diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d08264537af..625582373f3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -972,9 +972,9 @@ ;; special V1TI container class, which it is not appropriate to use vec_select ;; for the type. (define_insn "*vsx_le_permute_" - [(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=,,Z,&r,&r,Q") + [(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=wa,wa,Z,&r,&r,Q") (rotate:VSX_TI - (match_operand:VSX_TI 1 "input_operand" ",Z,,r,Q,r") + (match_operand:VSX_TI 1 "input_operand" "wa,Z,wa,r,Q,r") (const_int 64)))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "@ @@ -988,10 +988,10 @@ (set_attr "type" "vecperm,vecload,vecstore,*,load,store")]) (define_insn_and_split "*vsx_le_undo_permute_" - [(set (match_operand:VSX_TI 0 "vsx_register_operand" "=,") + [(set (match_operand:VSX_TI 0 "vsx_register_operand" "=wa,wa") (rotate:VSX_TI (rotate:VSX_TI - (match_operand:VSX_TI 1 "vsx_register_operand" "0,") + (match_operand:VSX_TI 1 "vsx_register_operand" "0,wa") (const_int 64)) (const_int 64)))] "!BYTES_BIG_ENDIAN && TARGET_VSX"