From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 20 Nov 2019 21:28:55 +0000 (-0800)
Subject: Add multi clock test
X-Git-Tag: working-ls180~881^2^2~165
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cd9e830b67fdffcae88dba095548995a30988fa4;p=yosys.git

Add multi clock test
---

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 64b625efe..1844bac20 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -267,3 +267,8 @@ module abc9_test026(output [3:0] o, p);
 assign o = { 1'b1, 1'bx };
 assign p = { 1'b1, 1'bx, 1'b0 };
 endmodule
+
+module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
+always @(posedge clk1) q1 <= d;
+always @(negedge clk2) q2 <= q1;
+endmodule