From: mePy2 <mePy2@web>
Date: Mon, 29 Mar 2021 10:41:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1101
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cdaf37d320d37425ddd871eb485c12e92603c1ae;p=libreriscv.git

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diff --git a/resources.mdwn b/resources.mdwn
index 6c5a54bb1..477aece5e 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -460,6 +460,21 @@ This list auto-generated from a page tag "standards":
 
 * [[resources/high-speed-serdes-in-circuitjs]]
 
+# Logic Simulator 2
+* <https://github.com/dkilfoyle/logic2>  
+[Live web version](https://dkilfoyle.github.io/logic2/)
+
+> ## Features   
+> 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)  
+> 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints  
+> 3. IDE docking ui courtesy of JupyterLab's Lumino widgets  
+> 4. Schematic visualisation courtesy of d3-hwschematic  
+> 5. Testbench simulation with graphical trace output and schematic animation  
+> 6. Circuit description as gates, boolean logic or verilog behavioural model  
+> 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
+ 
+[from the GitHub page. As of 2021/03/29]
+
 # ASIC Timing and Design flow resources
 
 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>