From: whitequark <whitequark@whitequark.org>
Date: Mon, 18 Nov 2019 09:37:14 +0000 (+0000)
Subject: Merge pull request #1494 from whitequark/write_verilog-extmem
X-Git-Tag: working-ls180~960
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cdb566b2d6a998ccaf5406f584e3ec810973dff9;p=yosys.git

Merge pull request #1494 from whitequark/write_verilog-extmem

write_verilog: add -extmem option, to write split memory init files
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cdb566b2d6a998ccaf5406f584e3ec810973dff9