From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 21 Aug 2016 11:45:46 +0000 (+0200)
Subject: Added another mem2reg test case
X-Git-Tag: yosys-0.7~115
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cdd0b85e47d6c1718ec5c0d2d80c87af3e3bbc83;p=yosys.git

Added another mem2reg test case
---

diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 23094c10a..9839fd4a8 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -81,3 +81,14 @@ module mem2reg_test4(result1, result2, result3);
 	assign result3 = intermediate[depth2Index(3)];
 endmodule
 
+// ------------------------------------------------------
+
+module mem2reg_test5(input ctrl, output out);
+	wire [0:0] foo[0:0];
+	wire [0:0] bar[0:1];
+
+	assign foo[0] = ctrl;
+	assign bar[0] = 0, bar[1] = 1;
+	assign out = bar[foo[0]];
+endmodule
+