From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 16 Jun 2019 01:18:56 +0000 (-0700)
Subject: Cleanup
X-Git-Tag: working-ls180~881^2^2~310
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cdfb634977b3ee005c5635f7902ea21dd45f7311;p=yosys.git

Cleanup
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index cedbc9273..e13cd0eef 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -671,26 +671,23 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		int in_wires = 0, out_wires = 0;
 
 		// Stitch in mapped_mod's inputs/outputs into module
-		// TODO: iterate using ports
-		for (auto &it : mapped_mod->wires_) {
-			RTLIL::Wire *w = it.second;
-			if (!w->port_input && !w->port_output)
-				continue;
-			RTLIL::Wire *wire = module->wire(w->name);
+		for (auto port_name : mapped_mod->ports) {
+			RTLIL::Wire *port = mapped_mod->wire(port_name);
+			log_assert(port);
+			RTLIL::Wire *wire = module->wire(port->name);
 			log_assert(wire);
-			RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
+			RTLIL::Wire *remap_wire = module->wire(remap_name(port->name));
 			RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
 			log_assert(GetSize(signal) >= GetSize(remap_wire));
 
-			log_assert(w->port_input || w->port_output);
 			RTLIL::SigSig conn;
-			if (w->port_input) {
+			if (port->port_input) {
 				conn.first = remap_wire;
 				conn.second = signal;
 				in_wires++;
 				module->connect(conn);
 			}
-			if (w->port_output) {
+			if (port->port_output) {
 				conn.first = signal;
 				conn.second = remap_wire;
 				out_wires++;