From: Cesar Strauss <cestrauss@gmail.com>
Date: Thu, 31 Dec 2020 20:31:41 +0000 (-0300)
Subject: Test first input port being masked out
X-Git-Tag: 24jan2021_ls180~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce0b77ae27014cbcc2972b4894cea99aaef222d4;p=soc.git

Test first input port being masked out
---

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index f27a2500..3e295935 100644
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -458,8 +458,8 @@ def scoreboard_sim(op):
     yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80],
                         rdmaskn=[0, 1],
                         src_delays=[2, 1], dest_delays=[0])
-    # 0 (masked) + 2 = 2
-    yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
+    # sign_extend(0x80) = 0xFF80
+    yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80],
                         rdmaskn=[1, 0],
                         src_delays=[1, 2], dest_delays=[1])
     # 0 (masked) + 0 (masked) = 0