From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 20 Feb 2022 01:04:53 +0000 (+0000)
Subject: add name to DFI Interface (helps gtkwave traces)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce19ad035d8a960cb0ca786b299f80da738e22e8;p=gram.git

add name to DFI Interface (helps gtkwave traces)
---

diff --git a/gram/dfii.py b/gram/dfii.py
index f3e9884..07a0a21 100644
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -61,9 +61,15 @@ class DFIInjector(Elaboratable):
     def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
         self._nranks = nranks
 
-        self._inti = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
-        self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
-        self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases)
+        self._inti = dfi.Interface(addressbits, bankbits,
+                                   nranks, databits, nphases,
+                                   name="inti")
+        self.slave = dfi.Interface(addressbits, bankbits,
+                                   nranks, databits, nphases,
+                                   name="slave")
+        self.master = dfi.Interface(addressbits, bankbits,
+                                    nranks, databits, nphases,
+                                   name="master")
 
         self._control = csr_bank.csr(4, "w")  # sel, clk_en, odt, reset
 
diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py
index 7e58b99..c2bdbbf 100644
--- a/gram/phy/dfi.py
+++ b/gram/phy/dfi.py
@@ -32,11 +32,13 @@ def phase_description(addressbits, bankbits, nranks, databits):
 
 
 class Interface:
-    def __init__(self, addressbits, bankbits, nranks, databits, nphases=1):
+    def __init__(self, addressbits, bankbits, nranks, databits, nphases=1,
+                       name=None):
         self.phases = []
         for p in range(nphases):
-            p = Record(phase_description(
-                addressbits, bankbits, nranks, databits))
+            p = Record(phase_description(addressbits, bankbits,
+                                         nranks, databits),
+                       name=name)
             self.phases += [p]
             p.reset.reset = 1