From: Mike Frysinger <vapier@gentoo.org>
Date: Wed, 22 Jun 2011 04:21:29 +0000 (+0000)
Subject: sim: bfin: pass up result2/errcode with libgloss syscalls
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce2486ab207e98f04931bc0f562ed4807258344a;p=binutils-gdb.git

sim: bfin: pass up result2/errcode with libgloss syscalls

Now that the Blackfin libgloss code extracts the 2nd result and the
error code from the R1/R2 registers, have the sim fill them up.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index 92d968a8318..a504f7a38ea 100644
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,8 @@
+2011-06-22  Mike Frysinger  <vapier@gentoo.org>
+
+	* interp.c (bfin_syscall): Delete old comment.  Set dreg 1 to
+	sc.result2 and dreg 2 to sc.errcode.
+
 2011-06-18  Robin Getz  <robin.getz@analog.com>
 
 	* bfin-sim.c (decode_dsp32shift_0): Clear ASTAT[AV] if val is 0,
diff --git a/sim/bfin/interp.c b/sim/bfin/interp.c
index d0a4e229c8a..583b82e0e80 100644
--- a/sim/bfin/interp.c
+++ b/sim/bfin/interp.c
@@ -594,8 +594,8 @@ bfin_syscall (SIM_CPU *cpu)
     {
       tbuf += sprintf (tbuf, "%lu (error = %i)", sc.result, sc.errcode);
       SET_DREG (0, sc.result);
-      /* Blackfin libgloss only expects R0 to be updated, not R1.  */
-      /*SET_DREG (1, sc.errcode);*/
+      SET_DREG (1, sc.result2);
+      SET_DREG (2, sc.errcode);
     }
 
   TRACE_SYSCALL (cpu, "%s", _tbuf);