From: Jose Maria Casanova Crespo Date: Wed, 12 Jul 2017 12:49:41 +0000 (+0200) Subject: i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce2e572c4c1b1f16e0b68923713001651b3f9bca;p=mesa.git i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg Currently, we use byte-scattered write messages for storing 16-bit into an SSBO. This is because untyped surface messages have a fixed 32-bit size. This patch optimizes these 16-bit writes by combining 2 values (e.g, two consecutive components aligned with 32-bits) into a 32-bit register, packing the two 16-bit words. 16-bit single component values will continue to use byte-scattered write messages. The same will happens when the first consecutive component is not aligned 32-bits. This optimization reduces the number of SEND messages used for storing 16-bit values potentially by 2 or 4, which cuts down execution time significantly because byte-scattered writes are an expensive operation as they only write a component for message. v2: Removed use of stride = 2 on sources (Jason Ekstrand) Rework optimization using shuffle 16 write and enable writes of 16bit vec4 with only one message of 32-bits. (Chema Casanova) v3: - Fix coding style (Eduardo Lima) - Reorganize code to avoid duplication. (Jason Ekstrand) - Include new comments to explain the length calculations to fix alignment issues of components. (Jason Ekstrand) - Fix issues with writemask yz with 16-bit writes. (Jason Ektrand) v4: (Jason Ekstrand) - Reorganize 64-bit ssbo-writes to avoid using slots_per_component. - Comment about why suffle is needed when using byte_scattered_write. Signed-off-by: Eduardo Lima Signed-off-by: Jose Maria Casanova Crespo Reviewed-by: Jason Ekstrand --- diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index aa4a8c4b8b3..e11e75e6332 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -4089,10 +4089,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr */ unsigned bit_size = nir_src_bit_size(instr->src[0]); unsigned type_size = bit_size / 8; - if (bit_size == 64) { - val_reg = shuffle_64bit_data_for_32bit_write(bld, - val_reg, instr->num_components); - } /* Combine groups of consecutive enabled channels in one write * message. We use ffs to find the first enabled channel and then ffs on @@ -4102,6 +4098,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr while (writemask) { unsigned first_component = ffs(writemask) - 1; unsigned num_components = ffs(~(writemask >> first_component)) - 1; + fs_reg write_src = offset(val_reg, bld, first_component); if (type_size > 4) { /* We can't write more than 2 64-bit components at once. Limit @@ -4109,12 +4106,45 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr * iteration handle the rest. */ num_components = MIN2(2, num_components); + write_src = shuffle_64bit_data_for_32bit_write(bld, write_src, + num_components); } else if (type_size < 4) { - /* For 16-bit types we are using byte scattered writes, that can - * only write one component per call. So we limit the num_components, - * and let the write happening in several iterations. + assert(type_size == 2); + /* For 16-bit types we pack two consecutive values into a 32-bit + * word and use an untyped write message. For single values or not + * 32-bit-aligned we need to use byte-scattered writes because + * untyped writes works with 32-bit components with 32-bit + * alignment. byte_scattered_write messages only support one + * 16-bit component at a time. + * + * For example, if there is a 3-components vector we submit one + * untyped-write message of 32-bit (first two components), and one + * byte-scattered write message (the last component). + */ + + if (first_component % 2) { + /* If we use a .yz writemask we also need to emit 2 + * byte-scattered write messages because of y-component not + * being aligned to 32-bit. + */ + num_components = 1; + } else if (num_components > 2 && (num_components % 2)) { + /* If there is an odd number of consecutive components we left + * the not paired component for a following emit of length == 1 + * with byte_scattered_write. + */ + num_components --; + } + /* For num_components == 1 we are also shuffling the component + * because byte scattered writes of 16-bit need values to be dword + * aligned. Shuffling only one component would be the same as + * striding it. */ - num_components = 1; + fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D, + DIV_ROUND_UP(num_components, 2)); + shuffle_16bit_data_for_32bit_write(bld, tmp, write_src, + num_components); + write_src = tmp; } fs_reg offset_reg; @@ -4129,7 +4159,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr brw_imm_ud(type_size * first_component)); } - if (type_size < 4) { + if (type_size < 4 && num_components == 1) { + assert(type_size == 2); /* Untyped Surface messages have a fixed 32-bit size, so we need * to rely on byte scattered in order to write 16-bit elements. * The byte_scattered_write message needs that every written 16-bit @@ -4148,11 +4179,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr pred = BRW_PREDICATE_NORMAL; } - fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D); - bld.MOV(subscript(tmp, BRW_REGISTER_TYPE_W, 0), - offset(val_reg, bld, first_component)); emit_byte_scattered_write(bld, surf_index, offset_reg, - tmp, + write_src, 1 /* dims */, 1, bit_size, pred); @@ -4160,10 +4188,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr assert(num_components * type_size <= 16); assert((num_components * type_size) % 4 == 0); assert((first_component * type_size) % 4 == 0); - unsigned first_slot = (first_component * type_size) / 4; unsigned num_slots = (num_components * type_size) / 4; + emit_untyped_write(bld, surf_index, offset_reg, - offset(val_reg, bld, first_slot), + write_src, 1 /* dims */, num_slots, BRW_PREDICATE_NONE); }