From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 29 Oct 2006 06:59:30 +0000 (-0500)
Subject: Fixed ldstub to use the right format, and made the load/store operations use the... 
X-Git-Tag: m5_2.0_beta2~70^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce313a15d5310aa8ee4412014e129ae26e7d18dc;p=gem5.git

Fixed ldstub to use the right format, and made the load/store operations use the integer microcode register.

--HG--
extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
---

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index dc7597e5e..aa3b6de6f 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -851,16 +851,15 @@ decode OP default Unknown::unknown()
             0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
             0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
             0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
-            0x0D: ldstub({{
-                Rd = Mem.ub;
-                Mem.ub = 0xFF;
-            }});
         }
+        0x0D: LoadStore::ldstub(
+        {{Rd = Mem.ub;}},
+        {{Mem.ub = 0xFF;}});
         0x0E: Store::stx({{Mem.udw = Rd}});
         0x0F: LoadStore::swap(
-            {{*temp = Rd.uw;
+            {{uReg0 = Rd.uw;
             Rd.uw = Mem.uw;}},
-            {{Mem.uw = *temp;}});
+            {{Mem.uw = uReg0;}});
         format Load {
             0x10: lduwa({{Rd = Mem.uw;}});
             0x11: lduba({{Rd = Mem.ub;}});
@@ -888,9 +887,9 @@ decode OP default Unknown::unknown()
                 {{Mem.ub = 0xFF}});
         0x1E: Store::stxa({{Mem.udw = Rd}});
         0x1F: LoadStore::swapa(
-            {{*temp = Rd.uw;
+            {{uReg0 = Rd.uw;
             Rd.uw = Mem.uw;}},
-            {{Mem.uw = *temp;}});
+            {{Mem.uw = uReg0;}});
         format Trap {
             0x20: Load::ldf({{Frd.uw = Mem.uw;}});
             0x21: decode X {