From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 15 May 2020 18:51:00 +0000 (-0400)
Subject: Add ability to specify initial CR state
X-Git-Tag: div_pipeline~1181
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce551dc62cbedf0c3cc4fa13d163162b4736df4b;p=soc.git

Add ability to specify initial CR state
---

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index 607cd6bd..9bb4b2b5 100644
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -55,6 +55,20 @@ class BranchMainStage(PipeModBase):
         with m.Else():
             comb += branch_addr.eq(branch_imm_addr + self.i.cia)
 
+
+        # handle conditional branches (BO and BI are same for BC and
+        # BCREG)
+        b_fields = self.fields.instrs['B']
+        bo = Signal(b_fields['BO'][0:-1].shape())
+        comb += bo.eq(b_fields['BO'][0:-1])
+        bi = Signal(b_fields['BI'][0:-1].shape())
+        comb += bi.eq(b_fields['BI'][0:-1])
+
+        cr_bit = Signal(reset_less=True)
+        comb += cr_bit.eq((self.i.cr & (1<<bi)) != 0)
+
+            
+
         with m.Switch(op.insn_type):
             with m.Case(InternalOp.OP_B):
                 li = Signal(i_fields['LI'][0:-1].shape())
@@ -64,6 +78,8 @@ class BranchMainStage(PipeModBase):
                     Cat(Const(0, 2), li,
                         Repl(li_sgn, 64-(li.width + 2))))
                 comb += branch_taken.eq(1)
+            with m.Case(InternalOp.OP_BC):
+                pass
 
         comb += self.o.nia_out.data.eq(branch_addr)
         comb += self.o.nia_out.ok.eq(branch_taken)
diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py
index 0a158081..bbebf613 100644
--- a/src/soc/branch/test/test_pipe_caller.py
+++ b/src/soc/branch/test/test_pipe_caller.py
@@ -19,11 +19,12 @@ import random
 
 
 class TestCase:
-    def __init__(self, program, regs, sprs, name):
+    def __init__(self, program, regs, sprs, cr, name):
         self.program = program
         self.regs = regs
         self.sprs = sprs
         self.name = name
+        self.cr = cr
 
 def get_rec_width(rec):
     recwidth = 0
@@ -59,8 +60,10 @@ class BranchTestCase(FHDLTestCase):
     def __init__(self, name):
         super().__init__(name)
         self.test_name = name
-    def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
-        tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
+    def run_tst_program(self, prog, initial_regs=[0] * 32,
+                        initial_sprs={}, initial_cr=0):
+        tc = TestCase(prog, initial_regs, initial_sprs, initial_cr,
+                      self.test_name)
         test_data.append(tc)
 
     def test_unconditional(self):
@@ -72,6 +75,12 @@ class BranchTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             self.run_tst_program(Program(lst), initial_regs)
 
+    @unittest.skip("broken")
+    def test_bc(self):
+        lst = ["bc 12, 2, 0x1234"]
+        self.run_tst_program(Program(lst), initial_cr=0xffffffff)
+        
+
     def test_ilang(self):
         rec = CompALUOpSubset()
 
@@ -113,7 +122,7 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs)
+                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
                 initial_cia = 0x2000
                 simulator.set_pc(initial_cia)
                 gen = program.generate_instructions()
diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 53b29c09..e7f26a63 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -167,7 +167,7 @@ class SPR(dict):
 class ISACaller:
     # decoder2 - an instance of power_decoder2
     # regfile - a list of initial values for the registers
-    def __init__(self, decoder2, regfile, initial_sprs={}):
+    def __init__(self, decoder2, regfile, initial_sprs={}, initial_cr=0):
         self.gpr = GPR(decoder2, regfile)
         self.mem = Mem()
         self.pc = PC()
@@ -186,7 +186,7 @@ class ISACaller:
         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 
         # create CR then allow portions of it to be "selectable" (below)
-        self._cr = SelectableInt(0, 64) # underlying reg
+        self._cr = SelectableInt(initial_cr, 64) # underlying reg
         self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 
         # "undefined", just set to variable-bit-width int (use exts "max")
diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 95eb13c7..1fa845d3 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -116,8 +116,8 @@ class PyISAWriter(ISA):
 
             classes = ', '.join(['ISACaller'] + self.pages_written)
             f.write('class ISA(%s):\n' % classes)
-            f.write('    def __init__(self, dec, regs, sprs):\n')
-            f.write('        super().__init__(dec, regs, sprs)\n')
+            f.write('    def __init__(self, dec, regs, sprs, cr):\n')
+            f.write('        super().__init__(dec, regs, sprs, cr)\n')
             f.write('        self.instrs = {\n')
             for page in self.pages_written:
                 f.write('            **self.%s_instrs,\n' % page)