From: Alberto Gonzalez Date: Mon, 20 Apr 2020 22:55:11 +0000 (+0000) Subject: Replace `std::set`s using custom comparators with `pool`. X-Git-Tag: working-ls180~517^2~6 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce62d0751ac25211cd468ae7026805e6933e0ce6;p=yosys.git Replace `std::set`s using custom comparators with `pool`. Co-Authored-By: Eddie Hung --- diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 6513ab827..16bc9c803 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -65,7 +65,7 @@ struct TechmapWorker dict simplemap_mappers; dict>, RTLIL::Module*> techmap_cache; dict techmap_do_cache; - std::set> module_queue; + pool module_queue; dict sigmaps; pool flatten_do_list; @@ -465,7 +465,7 @@ struct TechmapWorker } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, - const dict> &celltypeMap, bool in_recursion) + const dict> &celltypeMap, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -1305,7 +1305,7 @@ struct TechmapPass : public Pass { log_header(design, "Continuing TECHMAP pass.\n"); - dict> celltypeMap; + dict> celltypeMap; for (auto module : map->modules()) { if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) { char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str()); @@ -1386,7 +1386,7 @@ struct FlattenPass : public Pass { extra_args(args, argidx, design); - dict> celltypeMap; + dict> celltypeMap; for (auto module : design->modules()) celltypeMap[module->name].insert(module->name);