From: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Tue, 10 Oct 2017 00:42:59 +0000 (-0400)
Subject: nv50/ir: fix 64-bit integer shifts
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce6da2a02632cc81373b5e26881c02872e80c30b;p=mesa.git

nv50/ir: fix 64-bit integer shifts

TGSI was adjusted to always pass in 64-bit integers but nouveau was left
with the old semantics. Update to the new thing.

Fixes: d10fbe5159 (st/glsl_to_tgsi: fix 64-bit integer bit shifts)
Reported-by: Karol Herbst <karolherbst@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
---

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 27806057c5b..34351dab518 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -4028,7 +4028,9 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
          tmp[0] = fetchSrc(0, c);
          tmp[1] = fetchSrc(0, c + 1);
          mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
-         src1 = fetchSrc(1, c / 2);
+         // Theoretically src1 is a 64-bit value but in practice only the low
+         // bits matter. The IR expects this to be a 32-bit value.
+         src1 = fetchSrc(1, c);
          mkOp2(op, dstTy, dst, src0, src1);
          mkSplit(&dst0[c], 4, dst);
          c++;