From: lkcl Date: Tue, 17 Nov 2020 14:16:20 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1745 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce6e167822632aeafadb0a385b928a460a8e5404;p=libreriscv.git --- diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn index 14bc058bd..0f197e34c 100644 --- a/openpower/sv/16_bit_compressed.mdwn +++ b/openpower/sv/16_bit_compressed.mdwn @@ -10,9 +10,9 @@ EXT001, with some inconvenience (extra gates). The incompatibility is (v3.1B) Mode, at runtime, as needed. Although initially intended to be augmented by Simple-V Prefixing, to -add Vector context and predication yet not put pressure on I-Cache power +add Vector context, width overrides (e.g IEEE754 FP16) and predication yet not put pressure on I-Cache power or size, this Compressed Encoding is not critically dependent -*on* SV Prefixing, and may be used stand-alone +*on* SV Prefixing, and may be used stand-alone. See: @@ -261,19 +261,17 @@ is "nop" | 16-bit mode | | 10-bit mode | | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f | | N | 0 | RT | | 010.0 | RB | RA!=0 | M | add - | N | 0 | RT | | 010.1 | RB | RA | M | mul - | N | 0 | RT!=0 | | 011.0 | RB | RA!=0 | M | sub. - | N | 0 | 000 | | 011.0 | RB | RA!=0 | M | cmpw - | N | 0 | RT | | 011.0 | RB | 000 | M | neg. + | N | 0 | RT | | 010.1 | RB | RA | M | sub. + | N | 0 | RT!=0 | | 010.1 | RB | 000 | M | neg. + | N | 0 | 000 | | 010.1 | RB | 000 | M | + | N | 0 | BF | | 011.0 | RB | RA|0 | M | cmpl 16 bit mode only: | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f | - | N | 1 | RT | | 010.0 | | | M | - | N | 1 | RT | | 010.1 | RB | RA | M | div - | N | 1 | RT!=0 | | 011.0 | RB | RA!=0 | M | - | N | 1 | 000 | | 011.0 | RB | RA!=0 | M | cmpl - | N | 1 | RT | | 011.0 | RB | 000 | M | + | N | 1 | RT | | 010.0 | | | 0 | + | N | 1 | RT | | 010.1 | | | 0 | + | N | 1 | BF | | 011.0 | RB | RA|0 | 0 | cmpw 10 bit mode: @@ -300,14 +298,14 @@ is "nop" 16-bit mode only: | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f | - | N | 1 | RT | | 100.0 | RB | RA!=0 | M | - | N | 1 | RT | | 100.1 | RB | RA!=0 | M | - | N | 1 | RT | | 101.0 | RB | RA!=0 | M | xor - | N | 1 | RT | | 101.1 | RB | RA!=0 | M | eqv (xnor) - | N | 1 | RT | | 100.0 | RB | 0 0 0 | M | extsb - | N | 1 | RT | | 100.1 | RB | 0 0 0 | M | cnttz - | N | 1 | RT | | 101.0 | RB | 0 0 0 | M | - | N | 1 | RT | | 101.1 | RB | 0 0 0 | M | extsh + | N | 1 | RT | | 100.0 | RB | RA!=0 | 0 | + | N | 1 | RT | | 100.1 | RB | RA!=0 | 0 | + | N | 1 | RT | | 101.0 | RB | RA!=0 | 0 | xor + | N | 1 | RT | | 101.1 | RB | RA!=0 | 0 | eqv (xnor) + | N | 1 | RT | | 100.0 | RB | 0 0 0 | 0 | extsb + | N | 1 | RT | | 100.1 | RB | 0 0 0 | 0 | cnttz + | N | 1 | RT | | 101.0 | RB | 0 0 0 | 0 | + | N | 1 | RT | | 101.1 | RB | 0 0 0 | 0 | extsh 10 bit mode: @@ -332,12 +330,12 @@ Note here that elwidth overrides (SV Prefix) can be used to select FP16/32/64 16-bit mode only: | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f | - | N | 1 | RT | | 011.1 | RB | RA!=0 | M | - | N | 1 | RT | | 110.0 | RB | RA!=0 | M | - | N | 1 | RT | | 110.1 | RB | RA!=0 | M | fdiv - | N | 1 | RT | | 011.1 | RB | 0 0 0 | M | fabs. - | N | 1 | RT | | 110.0 | RB | 0 0 0 | M | fmr. - | N | 1 | RT | | 110.1 | RB | 0 0 0 | M | + | N | 1 | RT | | 011.1 | RB | RA!=0 | 0 | + | N | 1 | RT | | 110.0 | RB | RA!=0 | 0 | + | N | 1 | RT | | 110.1 | RB | RA!=0 | 0 | fdiv + | N | 1 | RT | | 011.1 | RB | 0 0 0 | 0 | fabs. + | N | 1 | RT | | 110.0 | RB | 0 0 0 | 0 | fmr. + | N | 1 | RT | | 110.1 | RB | 0 0 0 | 0 | 10 bit mode: