From: Jesse Natalie Date: Mon, 13 Apr 2020 14:50:37 +0000 (-0700) Subject: nir/vtn: Add type constant to image intrinsics X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce6f66242ad33be84c0a34519f18bdc15c195950;p=mesa.git nir/vtn: Add type constant to image intrinsics Since OpenCL supports untyped images, backends might need type info to be able to support the load/store ops. Reviewed-by: Jason Ekstrand Part-of: --- diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 9665a6c0ccb..12ce0dec2e6 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/glsl_to_nir.cpp @@ -1334,6 +1334,8 @@ nir_visitor::visit(ir_call *ir) } else if (op == nir_intrinsic_image_deref_load || op == nir_intrinsic_image_deref_store) { instr->num_components = 4; + nir_intrinsic_set_type(instr, + nir_get_nir_type_for_glsl_base_type(type->sampled_type)); } if (op == nir_intrinsic_image_deref_size || diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c index 2ef15300b65..aa259806d54 100644 --- a/src/compiler/nir/nir.c +++ b/src/compiler/nir/nir.c @@ -2291,6 +2291,9 @@ nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src, bool bindless) { enum gl_access_qualifier access = nir_intrinsic_access(intrin); + nir_alu_type type = nir_type_invalid; + if (nir_intrinsic_infos[intrin->intrinsic].index_map[NIR_INTRINSIC_TYPE]) + type = nir_intrinsic_type(intrin); switch (intrin->intrinsic) { #define CASE(op) \ @@ -2329,6 +2332,8 @@ nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src, nir_intrinsic_set_image_array(intrin, glsl_sampler_type_is_array(deref->type)); nir_intrinsic_set_access(intrin, access | var->data.access); nir_intrinsic_set_format(intrin, var->data.image.format); + if (nir_intrinsic_infos[intrin->intrinsic].index_map[NIR_INTRINSIC_TYPE]) + nir_intrinsic_set_type(intrin, type); nir_instr_rewrite_src(&intrin->instr, &intrin->src[0], nir_src_for_ssa(src)); diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index a48b76bac10..546428eeef3 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -386,16 +386,16 @@ atomic3("atomic_counter_comp_swap") # argument with the value to be written, and image atomic operations take # either one or two additional scalar arguments with the same meaning as in # the ARB_shader_image_load_store specification. -def image(name, src_comp=[], **kwargs): +def image(name, src_comp=[], extra_indices=[], **kwargs): intrinsic("image_deref_" + name, src_comp=[1] + src_comp, - indices=[ACCESS], **kwargs) + indices=[ACCESS] + extra_indices, **kwargs) intrinsic("image_" + name, src_comp=[1] + src_comp, - indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS], **kwargs) + indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) intrinsic("bindless_image_" + name, src_comp=[1] + src_comp, - indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS], **kwargs) + indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) -image("load", src_comp=[4, 1, 1], dest_comp=0, flags=[CAN_ELIMINATE]) -image("store", src_comp=[4, 1, 0, 1]) +image("load", src_comp=[4, 1, 1], extra_indices=[TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) +image("store", src_comp=[4, 1, 0, 1], extra_indices=[TYPE]) image("atomic_add", src_comp=[4, 1, 1], dest_comp=1) image("atomic_imin", src_comp=[4, 1, 1], dest_comp=1) image("atomic_umin", src_comp=[4, 1, 1], dest_comp=1) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 6dd18075c84..88b879cc89b 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -3133,17 +3133,20 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode, case SpvOpAtomicStore: case SpvOpImageWrite: { const uint32_t value_id = opcode == SpvOpAtomicStore ? w[4] : w[3]; - nir_ssa_def *value = vtn_get_nir_ssa(b, value_id); + struct vtn_ssa_value *value = vtn_ssa_value(b, value_id); /* nir_intrinsic_image_deref_store always takes a vec4 value */ assert(op == nir_intrinsic_image_deref_store); intrin->num_components = 4; - intrin->src[3] = nir_src_for_ssa(expand_to_vec4(&b->nb, value)); + intrin->src[3] = nir_src_for_ssa(expand_to_vec4(&b->nb, value->def)); /* Only OpImageWrite can support a lod parameter if * SPV_AMD_shader_image_load_store_lod is used but the current NIR * intrinsics definition for atomics requires us to set it for * OpAtomicStore. */ intrin->src[4] = nir_src_for_ssa(image.lod); + + if (opcode == SpvOpImageWrite) + nir_intrinsic_set_type(intrin, nir_get_nir_type_for_glsl_type(value->type)); break; } @@ -3196,6 +3199,9 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode, result = nir_channels(&b->nb, result, (1 << dest_components) - 1); vtn_push_nir_ssa(b, w[2], result); + + if (opcode == SpvOpImageRead) + nir_intrinsic_set_type(intrin, nir_get_nir_type_for_glsl_type(type->type)); } else { nir_builder_instr_insert(&b->nb, &intrin->instr); }