From: Andrew Cagney Date: Mon, 25 May 1998 05:48:34 +0000 (+0000) Subject: Fix mips SWL on 64bit ISA when 32 bit word appears in second half of X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce823781894cd9a9a61f7a446b40833f40bb01d3;p=binutils-gdb.git Fix mips SWL on 64bit ISA when 32 bit word appears in second half of 64 bit bus. Test. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 5a6a0e0819b..8c192d25f9b 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,10 @@ +Mon May 25 12:41:38 1998 Andrew Cagney + + * mips.igen (do_store_left, do_load_left): Compute nr of left and + right bits and then re-align left hand bytes to correct byte + lanes. Fix incorrect computation in do_store_left when loading + bytes from second word. + start-sanitize-tx3904 Fri May 22 13:34:20 1998 Andrew Cagney diff --git a/sim/testsuite/mips64r5900-elf/t-ldl.s b/sim/testsuite/mips64r5900-elf/t-ldl.s new file mode 100644 index 00000000000..1df0128e5f8 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/t-ldl.s @@ -0,0 +1,112 @@ +.include "t-macros.i" + + start + + .align 3 + .data +byteaddr: .word bytes + .align 7 +bytes: + .byte 0xb0 + .byte 0xb1 + .byte 0xb2 + .byte 0xb3 + .byte 0xb4 + .byte 0xb5 + .byte 0xb6 + .byte 0xb7 + .byte 0xb8 + .byte 0xb9 + .byte 0xba + .byte 0xbb + .byte 0xbc + .byte 0xbd + .byte 0xbe + .byte 0xbf + + .text + ld $8, byteaddr + + +test_ldl_0: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb0cccccccccccccc + +test_ldl_1: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 1($8) + check10 0xdeadbeefdeadbeef 0xb1b0cccccccccccc + +test_ldl_2: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 2($8) + check10 0xdeadbeefdeadbeef 0xb2b1b0cccccccccc + +test_ldl_3: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 3($8) + check10 0xdeadbeefdeadbeef 0xb3b2b1b0cccccccc + +test_ldl_4: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 4($8) + check10 0xdeadbeefdeadbeef 0xb4b3b2b1b0cccccc + +test_ldl_5: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 5($8) + check10 0xdeadbeefdeadbeef 0xb5b4b3b2b1b0cccc + +test_ldl_6: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 6($8) + check10 0xdeadbeefdeadbeef 0xb6b5b4b3b2b1b0cc + +test_ldl_7: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 7($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + + +test_ldl_8: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 8($8) + check10 0xdeadbeefdeadbeef 0xb8cccccccccccccc + +test_ldl_9: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 9($8) + check10 0xdeadbeefdeadbeef 0xb9b8cccccccccccc + +test_ldl_10: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 10($8) + check10 0xdeadbeefdeadbeef 0xbab9b8cccccccccc + +test_ldl_11: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 11($8) + check10 0xdeadbeefdeadbeef 0xbbbab9b8cccccccc + +test_ldl_12: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 12($8) + check10 0xdeadbeefdeadbeef 0xbcbbbab9b8cccccc + +test_ldl_13: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 13($8) + check10 0xdeadbeefdeadbeef 0xbdbcbbbab9b8cccc + +test_ldl_14: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 14($8) + check10 0xdeadbeefdeadbeef 0xbebdbcbbbab9b8cc + +test_ldl_15: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldl $10, 15($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/t-ldr.s b/sim/testsuite/mips64r5900-elf/t-ldr.s new file mode 100644 index 00000000000..774fbb1b98f --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/t-ldr.s @@ -0,0 +1,112 @@ +.include "t-macros.i" + + start + + .align 3 + .data +byteaddr: .word bytes + .align 7 +bytes: + .byte 0xb0 + .byte 0xb1 + .byte 0xb2 + .byte 0xb3 + .byte 0xb4 + .byte 0xb5 + .byte 0xb6 + .byte 0xb7 + .byte 0xb8 + .byte 0xb9 + .byte 0xba + .byte 0xbb + .byte 0xbc + .byte 0xbd + .byte 0xbe + .byte 0xbf + + .text + ld $8, byteaddr + + +test_ldr_0: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_ldr_1: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 1($8) + check10 0xdeadbeefdeadbeef 0xccb7b6b5b4b3b2b1 + +test_ldr_2: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 2($8) + check10 0xdeadbeefdeadbeef 0xccccb7b6b5b4b3b2 + +test_ldr_3: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 3($8) + check10 0xdeadbeefdeadbeef 0xccccccb7b6b5b4b3 + +test_ldr_4: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 4($8) + check10 0xdeadbeefdeadbeef 0xccccccccb7b6b5b4 + +test_ldr_5: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 5($8) + check10 0xdeadbeefdeadbeef 0xccccccccccb7b6b5 + +test_ldr_6: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 6($8) + check10 0xdeadbeefdeadbeef 0xccccccccccccb7b6 + +test_ldr_7: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 7($8) + check10 0xdeadbeefdeadbeef 0xccccccccccccccb7 + + +test_ldr_8: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_ldr_9: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 9($8) + check10 0xdeadbeefdeadbeef 0xccbfbebdbcbbbab9 + +test_ldr_10: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 10($8) + check10 0xdeadbeefdeadbeef 0xccccbfbebdbcbbba + +test_ldr_11: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 11($8) + check10 0xdeadbeefdeadbeef 0xccccccbfbebdbcbb + +test_ldr_12: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 12($8) + check10 0xdeadbeefdeadbeef 0xccccccccbfbebdbc + +test_ldr_13: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 13($8) + check10 0xdeadbeefdeadbeef 0xccccccccccbfbebd + +test_ldr_14: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 14($8) + check10 0xdeadbeefdeadbeef 0xccccccccccccbfbe + +test_ldr_15: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + ldr $10, 15($8) + check10 0xdeadbeefdeadbeef 0xccccccccccccccbf + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/t-lwl.s b/sim/testsuite/mips64r5900-elf/t-lwl.s new file mode 100644 index 00000000000..8bda059fcf0 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/t-lwl.s @@ -0,0 +1,65 @@ +.include "t-macros.i" + + start + + .align 3 + .data +byteaddr: .word bytes + .align 7 +bytes: + .byte 0xb0 + .byte 0xb1 + .byte 0xb2 + .byte 0xb3 + .byte 0xb4 + .byte 0xb5 + .byte 0xb6 + .byte 0xb7 + .byte 0xb8 + + + .text + ld $8, byteaddr + +test_lwl0: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwl $10, 0($8) + check10 0xdeadbeefdeadbeef 0xffffffffb0cccccc + +test_lwl1: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwl $10, 1($8) + check10 0xdeadbeefdeadbeef 0xffffffffb1b0cccc + +test_lwl2: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwl $10, 2($8) + check10 0xdeadbeefdeadbeef 0xffffffffb2b1b0cc + +test_lwl3: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwl $10, 3($8) + check10 0xdeadbeefdeadbeef 0xffffffffb3b2b1b0 + + +test_lwl4: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwl $10, 4($8) + check10 0xdeadbeefdeadbeef 0xffffffffb4cccccc + +test_lwl5: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwl $10, 5($8) + check10 0xdeadbeefdeadbeef 0xffffffffb5b4cccc + +test_lwl6: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwl $10, 6($8) + check10 0xdeadbeefdeadbeef 0xffffffffb6b5b4cc + +test_lwl7: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwl $10, 7($8) + check10 0xdeadbeefdeadbeef 0xffffffffb7b6b5b4 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/t-lwr.s b/sim/testsuite/mips64r5900-elf/t-lwr.s new file mode 100644 index 00000000000..efb1cbc9f23 --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/t-lwr.s @@ -0,0 +1,65 @@ +.include "t-macros.i" + + start + + .align 3 + .data +byteaddr: .word bytes + .align 7 +bytes: + .byte 0xb0 + .byte 0xb1 + .byte 0xb2 + .byte 0xb3 + .byte 0xb4 + .byte 0xb5 + .byte 0xb6 + .byte 0xb7 + .byte 0xb8 + + + .text + ld $8, byteaddr + +test_lwr_0: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwr $10, 0($8) + check10 0xdeadbeefdeadbeef 0xffffffffb3b2b1b0 + +test_lwr_1: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwr $10, 1($8) + check10 0xdeadbeefdeadbeef 0xffffffffccb3b2b1 + +test_lwr_2: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwr $10, 2($8) + check10 0xdeadbeefdeadbeef 0xffffffffccccb3b2 + +test_lwr_3: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwr $10, 3($8) + check10 0xdeadbeefdeadbeef 0xffffffffccccccb3 + + +test_lwr_4: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwr $10, 4($8) + check10 0xdeadbeefdeadbeef 0xffffffffb7b6b5b4 + +test_lwr_5: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwr $10, 5($8) + check10 0xdeadbeefdeadbeef 0xffffffffccb7b6b5 + +test_lwr_6: + load $10 0xdeadbeefdeadbeef 0xffffffffcccccccc + lwr $10, 6($8) + check10 0xdeadbeefdeadbeef 0xffffffffccccb7b6 + +test_lwr_7: + load $10 0xdeadbeefdeadbeef 0xcccccccccccccccc + lwr $10, 7($8) + check10 0xdeadbeefdeadbeef 0xffffffffccccccb7 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/t-sdr.s b/sim/testsuite/mips64r5900-elf/t-sdr.s new file mode 100644 index 00000000000..59c258729ed --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/t-sdr.s @@ -0,0 +1,159 @@ +.include "t-macros.i" + + start + + .align 3 + .data +byteaddr: .word bytes + .align 7 +bytes: + .byte 0xb0 + .byte 0xb1 + .byte 0xb2 + .byte 0xb3 + .byte 0xb4 + .byte 0xb5 + .byte 0xb6 + .byte 0xb7 + .byte 0xb8 + .byte 0xb9 + .byte 0xba + .byte 0xbb + .byte 0xbc + .byte 0xbd + .byte 0xbe + .byte 0xbf + + .text + ld $8, byteaddr + +test_sdr_0: + load $10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + sdr $10, 0($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_1: + load $10 0xdeadbeefdeadbeef 0xccb7b6b5b4b3b2b1 + sdr $10, 1($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_2: + load $10 0xdeadbeefdeadbeef 0xccccb7b6b5b4b3b2 + sdr $10, 2($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_3: + load $10 0xdeadbeefdeadbeef 0xccccccb7b6b5b4b3 + sdr $10, 3($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_4: + load $10 0xdeadbeefdeadbeef 0xccccccccb7b6b5b4 + sdr $10, 4($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_5: + load $10 0xdeadbeefdeadbeef 0xccccccccccb7b6b5 + sdr $10, 5($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_6: + load $10 0xdeadbeefdeadbeef 0xccccccccccccb7b6 + sdr $10, 6($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_7: + load $10 0xdeadbeefdeadbeef 0xccccccccccccccb7 + sdr $10, 7($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + + +test_sdr_8: + load $10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + sdr $10, 8($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_9: + load $10 0xdeadbeefdeadbeef 0xccbfbebdbcbbbab9 + sdr $10, 9($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_10: + load $10 0xdeadbeefdeadbeef 0xccccbfbebdbcbbba + sdr $10, 10($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_11: + load $10 0xdeadbeefdeadbeef 0xccccccbfbebdbcbb + sdr $10, 11($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_12: + load $10 0xdeadbeefdeadbeef 0xccccccccbfbebdbc + sdr $10, 12($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_13: + load $10 0xdeadbeefdeadbeef 0xccccccccccbfbebd + sdr $10, 13($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_14: + load $10 0xdeadbeefdeadbeef 0xccccccccccccbfbe + sdr $10, 14($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + +test_sdr_15: + load $10 0xdeadbeefdeadbeef 0xccccccccccccccbf + sdr $10, 15($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + ld $10, 8($8) + check10 0xdeadbeefdeadbeef 0xbfbebdbcbbbab9b8 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/t-swl.s b/sim/testsuite/mips64r5900-elf/t-swl.s new file mode 100644 index 00000000000..3edbb2ba05b --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/t-swl.s @@ -0,0 +1,73 @@ +.include "t-macros.i" + + start + + .align 3 + .data +byteaddr: .word bytes + .align 7 +bytes: + .byte 0xb0 + .byte 0xb1 + .byte 0xb2 + .byte 0xb3 + .byte 0xb4 + .byte 0xb5 + .byte 0xb6 + .byte 0xb7 + .byte 0xb8 + + + .text + ld $8, byteaddr + +test_swl_0: + load $10 0xdeadbeefdeadbeef 0xffffffffb0cccccc + swl $10, 0($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swl_1: + load $10 0xdeadbeefdeadbeef 0xffffffffb1b0cccc + swl $10, 1($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swl_2: + load $10 0xdeadbeefdeadbeef 0xffffffffb2b1b0cc + swl $10, 2($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swl_3: + load $10 0xdeadbeefdeadbeef 0xffffffffb3b2b1b0 + swl $10, 3($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + + +test_swl_4: + load $10 0xdeadbeefdeadbeef 0xffffffffb4cccccc + swl $10, 4($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swl_5: + load $10 0xdeadbeefdeadbeef 0xffffffffb5b4cccc + swl $10, 5($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swl_6: + load $10 0xdeadbeefdeadbeef 0xffffffffb6b5b4cc + swl $10, 6($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swl_7: + load $10 0xdeadbeefdeadbeef 0xffffffffb7b6b5b4 + swl $10, 7($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + + exit0 diff --git a/sim/testsuite/mips64r5900-elf/t-swr.s b/sim/testsuite/mips64r5900-elf/t-swr.s new file mode 100644 index 00000000000..e51d2eb9eee --- /dev/null +++ b/sim/testsuite/mips64r5900-elf/t-swr.s @@ -0,0 +1,73 @@ +.include "t-macros.i" + + start + + .align 3 + .data +byteaddr: .word bytes + .align 7 +bytes: + .byte 0xb0 + .byte 0xb1 + .byte 0xb2 + .byte 0xb3 + .byte 0xb4 + .byte 0xb5 + .byte 0xb6 + .byte 0xb7 + .byte 0xb8 + + + .text + ld $8, byteaddr + +test_swr_0: + load $10 0xdeadbeefdeadbeef 0xffffffffb3b2b1b0 + swr $10, 0($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swr_1: + load $10 0xdeadbeefdeadbeef 0xffffffffccb3b2b1 + swr $10, 1($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swr_2: + load $10 0xdeadbeefdeadbeef 0xffffffffccccb3b2 + swr $10, 2($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swr_3: + load $10 0xdeadbeefdeadbeef 0xffffffffccccccb3 + swr $10, 3($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + + +test_swr_4: + load $10 0xdeadbeefdeadbeef 0xffffffffb7b6b5b4 + swr $10, 4($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swr_5: + load $10 0xdeadbeefdeadbeef 0xffffffffccb7b6b5 + swr $10, 5($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swr_6: + load $10 0xdeadbeefdeadbeef 0xffffffffccccb7b6 + swr $10, 6($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + +test_swr_7: + load $10 0xdeadbeefdeadbeef 0xffffffffccccccb7 + swr $10, 7($8) + ld $10, 0($8) + check10 0xdeadbeefdeadbeef 0xb7b6b5b4b3b2b1b0 + + exit0