From: Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Date: Wed, 16 Apr 2008 15:31:33 +0000 (+0000)
Subject: <opcode changes>
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce886ab1f881e00ad77c6b1a41e351d7b47f2540;p=binutils-gdb.git

<opcode changes>
2008-04-16  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
            Michael Meissner  <michael.meissner@amd.com>

        * i386-opc.tbl: Fix protX to allow memory in the middle operand.
        * i386-tbl.h: Regenerate from i386-opc.tbl.

<gas/testsuite changes>
2008-04-16  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
            Michael Meissner  <michael.meissner@amd.com>

        * gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the middle
        operand.
        * gas/i386/x86-64-sse5.d: Likewise.
---

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6b0b555602f..3dcb5ca9cc2 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2008-04-16  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+	    Michael Meissner  <michael.meissner@amd.com>
+
+	* gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the middle 
+	operand.
+	* gas/i386/x86-64-sse5.d: Likewise.
+	
 2008-04-16  David S. Miller  <davem@davemloft.net>
 
 	* gas/sparc/gotops32.d: New.
diff --git a/gas/testsuite/gas/i386/x86-64-sse5.d b/gas/testsuite/gas/i386/x86-64-sse5.d
index cd3cb3dae6e..92b1c906bc2 100644
--- a/gas/testsuite/gas/i386/x86-64-sse5.d
+++ b/gas/testsuite/gas/i386/x86-64-sse5.d
@@ -2838,4 +2838,7 @@ Disassembly of section .text:
 [ 	]+48c8:[ 	]+41 0f 7a 30 8f 00 00 10 00[ 	]+cvtph2ps 0x100000\(%r15\),%xmm1
 [ 	]+48d1:[ 	]+0f 7a 31 d1[ 	]+cvtps2ph %xmm2,%xmm1
 [ 	]+48d5:[ 	]+41 0f 7a 31 8f 00 00 10 00[ 	]+cvtps2ph %xmm1,0x100000\(%r15\)
-[ 	]+48de:[ 	]+c3[ 	]+retq[ 	]*
+[ 	]+48de:[ 	]+0f 7b 40 41 04 04[ 	]+protb[ 	]+\$0x4,0x4\(%rcx\),%xmm0
+[ 	]+48e4:[ 	]+41 0f 7b 41 42 08 01[ 	]+protw[ 	]+\$0x1,0x8\(%r10\),%xmm0
+[ 	]+48eb:[ 	]+41 0f 7b 43 41 04 03[ 	]+protq[ 	]+\$0x3,0x4\(%r9\),%xmm0
+[ 	]+48f2:[ 	]+c3[ 	]+retq[ 	]*
diff --git a/gas/testsuite/gas/i386/x86-64-sse5.s b/gas/testsuite/gas/i386/x86-64-sse5.s
index 3c327b2e986..0926e45aa05 100644
--- a/gas/testsuite/gas/i386/x86-64-sse5.s
+++ b/gas/testsuite/gas/i386/x86-64-sse5.s
@@ -2966,5 +2966,9 @@ foo:
 	cvtps2ph        %xmm2, %xmm1
 	cvtps2ph        %xmm1, 0x100000(%r15)
 
+	protb           $0x4, 0x4(%rdx), %xmm1
+	protw		$0x1, 0x8(%r14), %xmm2
+	protq		$0x3, 0x4(%r15), %xmm1
+	
 	ret
 	.size	foo, .-foo
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f92aed199a9..7187955019e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2008-04-16  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+	    Michael Meissner  <michael.meissner@amd.com>
+
+	* i386-opc.tbl: Fix protX to allow memory in the middle operand.
+	* i386-tbl.h: Regenerate from i386-opc.tbl.
+	
 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 
 	* ppc-dis.c (powerpc_dialect): Handle "e500mc".  Extend "e500" to
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index e306158bd2c..004477583ee 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2523,13 +2523,13 @@ pperm, 4, 0x0f2423, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|N
 permps, 4, 0x0f2420, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 permpd, 4, 0x0f2421, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protb, 3, 0x0f2440, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protb, 3, 0x0f7b40, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,            { Imm8,            RegXMM,          RegXMM }
+protb, 3, 0x0f7b40, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protw, 3, 0x0f2441, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protw, 3, 0x0f7b41, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,            { Imm8,            RegXMM,          RegXMM }
+protw, 3, 0x0f7b41, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protd, 3, 0x0f2442, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protd, 3, 0x0f7b42, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,            { Imm8,            RegXMM,          RegXMM }
+protd, 3, 0x0f7b42, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8,  RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 protq, 3, 0x0f2443, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
-protq, 3, 0x0f7b43, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm,            { Imm8,            RegXMM,          RegXMM }
+protq, 3, 0x0f7b43, 0x0, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm, { Imm8, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlb, 3, 0x0f2444, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshlw, 3, 0x0f2445, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
 pshld, 3, 0x0f2446, None, 3, CpuSSE5, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Modrm|Drex|Drexv, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM|Disp8|Disp16|Disp32|Disp32S|BaseIndex|Xmmword|Unspecified, RegXMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 9523785134d..556f324c5dc 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -27560,8 +27560,8 @@ const template i386_optab[] =
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } },
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 0, 1, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
@@ -27590,8 +27590,8 @@ const template i386_optab[] =
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } },
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 0, 1, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
@@ -27620,8 +27620,8 @@ const template i386_optab[] =
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } },
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 0, 1, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },
@@ -27650,8 +27650,8 @@ const template i386_optab[] =
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-	  0, 0, 0, 0, 0, 0 } },
+	  1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
+	  1, 0, 1, 0, 0, 0 } },
       { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
 	  0, 0, 0, 0, 0, 0 } } } },