From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 31 May 2020 11:54:29 +0000 (+0100)
Subject: copy in cr0.data into cr0 temp, not whole of cr0 (including ok flag)
X-Git-Tag: div_pipeline~722
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ce89d5de655594f3d11563b1d6833c6dc174da71;p=soc.git

copy in cr0.data into cr0 temp, not whole of cr0 (including ok flag)
---

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 1faa1ee6..1b37a625 100644
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -55,7 +55,7 @@ class CommonOutputStage(PipeModBase):
         comb += is_negative.eq(~is_zero & msb_test)
 
         with m.If(is_cmpeqb):
-            comb += cr0.eq(self.i.cr0)
+            comb += cr0.eq(self.i.cr0.data)
         with m.Else():
             comb += cr0.eq(Cat(self.so, is_zero, is_positive, is_negative))