From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 13 May 2020 21:42:18 +0000 (-0700)
Subject: ecp5: latches_map.v if *not* -asyncprld
X-Git-Tag: working-ls180~549^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cea614f5aeb78446c663240103f94f10e71681e2;p=yosys.git

ecp5: latches_map.v if *not* -asyncprld
---

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b99cbdf83..e5c1f7550 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -330,8 +330,8 @@ struct SynthEcp5Pass : public ScriptPass
 		{
 			if (abc2 || help_mode)
 				run("abc", "      (only if -abc2)");
-			if (asyncprld || help_mode)
-				run("techmap -map +/ecp5/latches_map.v", "(only if -asyncprld)");
+			if (!asyncprld || help_mode)
+				run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)");
 
 			if (abc9) {
 				run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");