From: Eddie Hung Date: Thu, 9 Jan 2020 22:03:43 +0000 (-0800) Subject: write_xaiger: cleanup X-Git-Tag: working-ls180~822^2~26 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ceabd5bc3984a0ff088d697ac8ba7061b4f552fb;p=yosys.git write_xaiger: cleanup --- diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 1956422bc..cde53ff63 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -243,23 +243,21 @@ struct XAigerWriter if (port_wire->port_output) { arrivals.clear(); auto it = port_wire->attributes.find("\\abc9_arrival"); - if (it != port_wire->attributes.end()) { - if (it->second.flags == 0) - arrivals.emplace_back(it->second.as_int()); - else - for (const auto &tok : split_tokens(it->second.decode_string())) - arrivals.push_back(atoi(tok.c_str())); - } - if (!arrivals.empty()) { - if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) - log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), - GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); - auto jt = arrivals.begin(); - for (auto bit : sigmap(conn.second)) { - arrival_times[bit] = *jt; - if (arrivals.size() > 1) - jt++; - } + if (it == port_wire->attributes.end()) + continue; + if (it->second.flags == 0) + arrivals.emplace_back(it->second.as_int()); + else + for (const auto &tok : split_tokens(it->second.decode_string())) + arrivals.push_back(atoi(tok.c_str())); + if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) + log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), + GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); + auto jt = arrivals.begin(); + for (auto bit : sigmap(conn.second)) { + arrival_times[bit] = *jt; + if (arrivals.size() > 1) + jt++; } } }