From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 12 Jun 2020 10:42:22 +0000 (+0200)
Subject: Fix clock signal for ECP5 PHY
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cebd2d450901fa1e9150f7c345ae0140e7043d53;p=gram.git

Fix clock signal for ECP5 PHY
---

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 5e33983..289c001 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -275,7 +275,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                                      p_DQS_LO_DEL_ADJ="MINUS",
                                      p_DQS_LO_DEL_VAL=4,
                                      # Clocks / Reset
-                                     i_SCLK=ClockSignal("sys"),
+                                     i_SCLK=ClockSignal("sync"),
                                      i_ECLK=ClockSignal("sync2x"),
                                      i_RST=ResetSignal("sync2x"),
                                      i_DDRDEL=self.init.delay,