From: lkcl <lkcl@web>
Date: Sat, 10 Sep 2022 18:05:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~510
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cecc5b978b19735b0e3aeb460ac22b2ef54a6e1b;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 0c460d177..7de6d0439 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -72,6 +72,8 @@ is perfectly fine to implement Ultra-Embedded on AIX, and perfectly fine to impl
 This level exists to indicate the critical importance of all and any
 features attempted to be executed on hardware that has no support at
 all for Simple-V being **required** to raise Illegal Exceptions.
+**This includes existing Power ISA Implementations:** IBM POWER being
+the most notable.
 
 With parts of the Power ISA being "silent executed" (hints for example),
 it is absolutely critical to have all capabilities of Simple-V sit