From: Luke Kenneth Casson Leighton Date: Fri, 22 Jul 2022 15:12:31 +0000 (+0100) Subject: clarify vector register X-Git-Tag: opf_rfc_ls005_v1~1131 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ced2362fdfa5a7a9b70170395a96f8088b1d17db;p=libreriscv.git clarify vector register --- diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index c0bb36363..c7251c538 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -13,7 +13,7 @@ * {1}: plus EXT001 24-bit prefixing. See [[sv/svp64]] * {2}: A 2-Dimensional Scalable Vector ISA with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]] * {3}: on specific operations. See [[opcode_regs_deduped]] for full list -* {4}: SVP64 provides the Vector register concept on top of the **Scalar** GPR, FPR and CR register files. +* {4}: SVP64 provides the Vector register concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries. * {5}: SVP64 Vectorises Scalar instructions. It is up to the **implementor** to choose (**optionally**) whether to apply SVP64 to e.g. VSX Quad-Precision (128-bit) instructions. * {6}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations * {7} See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)