From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 5 Aug 2007 03:07:42 +0000 (-0700)
Subject: X86: Create a base enum value for indexing into a region of the miscregs.
X-Git-Tag: m5_2.0_beta4~202
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ced6cbcccf4540358093f060dad4d59ad6557d6a;p=gem5.git

X86: Create a base enum value for indexing into a region of the miscregs.
This lets you index into a group of registers without having to know
explicitly which one is the lowest in that group.

--HG--
extra : convert_revision : e3cad25a1c5910955204c37177b049ca9834cfd9
---

diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index 39425fc9d..b2294292e 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -77,7 +77,8 @@ namespace X86ISA
     {
         // Control registers
         // Most of these are invalid.
-        MISCREG_CR0,
+        MISCREG_CR_BASE,
+        MISCREG_CR0 = MISCREG_CR_BASE,
         MISCREG_CR1,
         MISCREG_CR2,
         MISCREG_CR3,
@@ -95,7 +96,8 @@ namespace X86ISA
         MISCREG_CR15,
 
         // Debug registers
-        MISCREG_DR0,
+        MISCREG_DR_BASE,
+        MISCREG_DR0 = MISCREG_DR_BASE,
         MISCREG_DR1,
         MISCREG_DR2,
         MISCREG_DR3,
@@ -108,7 +110,8 @@ namespace X86ISA
         MISCREG_RFLAGS,
 
         // Segment selectors
-        MISCREG_ES,
+        MISCREG_SEG_SEL_BASE,
+        MISCREG_ES = MISCREG_SEG_SEL_BASE,
         MISCREG_CS,
         MISCREG_SS,
         MISCREG_DS,
@@ -116,7 +119,8 @@ namespace X86ISA
         MISCREG_GS,
 
         // Hidden segment base field
-        MISCREG_ES_BASE,
+        MISCREG_SEG_BASE_BASE,
+        MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
         MISCREG_CS_BASE,
         MISCREG_SS_BASE,
         MISCREG_DS_BASE,
@@ -124,7 +128,8 @@ namespace X86ISA
         MISCREG_GS_BASE,
 
         // Hidden segment limit field
-        MISCREG_ES_LIMIT,
+        MISCREG_SEG_LIMIT_BASE,
+        MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
         MISCREG_CS_LIMIT,
         MISCREG_SS_LIMIT,
         MISCREG_DS_LIMIT,
@@ -132,7 +137,8 @@ namespace X86ISA
         MISCREG_GS_LIMIT,
 
         // Hidden segment limit attributes
-        MISCREG_ES_ATTR,
+        MISCREG_SEG_ATTR_BASE,
+        MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
         MISCREG_CS_ATTR,
         MISCREG_SS_ATTR,
         MISCREG_DS_ATTR,
@@ -140,23 +146,27 @@ namespace X86ISA
         MISCREG_GS_ATTR,
 
         // System segment selectors
-        MISCREG_LDTR,
+        MISCREG_SYSSEG_SEL_BASE,
+        MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
         MISCREG_TR,
 
         // Hidden system segment base field
-        MISCREG_LDTR_BASE,
+        MISCREG_SYSSEG_BASE_BASE,
+        MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
         MISCREG_TR_BASE,
         MISCREG_GDTR_BASE,
         MISCREG_IDTR_BASE,
 
         // Hidden system segment limit field
-        MISCREG_LDTR_LIMIT,
+        MISCREG_SYSSEG_LIMIT_BASE,
+        MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
         MISCREG_TR_LIMIT,
         MISCREG_GDTR_LIMIT,
         MISCREG_IDTR_LIMIT,
 
         // Hidden system segment attribute field
-        MISCREG_LDTR_ATTR,
+        MISCREG_SYSSEG_ATTR_BASE,
+        MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
         MISCREG_TR_ATTR,
 
         //XXX Add "Model-Specific Registers"