From: lkcl <lkcl@web>
Date: Fri, 25 Dec 2020 01:46:56 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~925
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ced8813325c8c2aee723486d4ce61ce273a978ed;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 0b4d5c706..d728a31e8 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -109,7 +109,7 @@ Single Predication therefore provides several modes traditionally seen in Vector
 
 # Predicate "zeroing" mode
 
-Sometimes with predication it is ok to leave the masked-out element alone (not modify the result) however sometimes it is better to zero the masked-out elements.  This can be combined with bit-wise ORing to build up vectors from multiple predicate patterns.  Our pseudocode therefore ends up as follows, to take that into account:
+Sometimes with predication it is ok to leave the masked-out element alone (not modify the result) however sometimes it is better to zero the masked-out elements.  Zeroing can be combined with bit-wise ORing to build up vectors from multiple predicate patterns: the same combining with nonzeroing involves more mv operations and predicate mask operations.  Our pseudocode therefore ends up as follows, to take the enhancement into account:
 
     function op_add(rd, rs1, rs2) # add not VADD!
       int id=0, irs1=0, irs2=0;
@@ -118,8 +118,8 @@ Sometimes with predication it is ok to leave the masked-out element alone (not m
         if (predval & 1<<i) # predication bit test
            ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
            if (!rd.isvec) break;
-        else if zeroing:
-           ireg[rd+id] = 0
+        else if zeroing:   # predicate failed
+           ireg[rd+id] = 0 # set element  to zero
         if (rd.isvec)  { id += 1; }
         if (rs1.isvec)  { irs1 += 1; }
         if (rs2.isvec)  { irs2 += 1; }