From: lkcl <lkcl@web>
Date: Sun, 5 Sep 2021 20:43:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~211
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cee2e5e99262ce2349e06a58e82eaf4bdc1c6756;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 88f3626f2..8137c0070 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -129,7 +129,7 @@ Brief description of fields:
 * **sz=1** if predication is enabled and `sz=1` and a predicate
   element bit is zero, `SNZ` will
   be substituted in place of the CR bit selected by `BI`.
-  the src CR Field when the predicate bit is zero. Contrast this with
+  Contrast this with
   normal SVP64 `sz=1` behaviour, where *only* a zero is put in
   place of masked-out predicate bits.
 * **sz=0** When `sz=0` skipping occurs as usual, but unlike all