From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 19:24:25 +0000 (-0700)
Subject: Mention shregmap -tech xilinx is superseded
X-Git-Tag: working-ls180~1085^2~46
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cee30deef5f48b97af961ecb6f7194eac14d891c;p=yosys.git

Mention shregmap -tech xilinx is superseded
---

diff --git a/CHANGELOG b/CHANGELOG
index b4b3005d4..5848ae705 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -29,7 +29,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Removed "ice40_unlut"
     - Improvements in pmgen: slices, choices, define, generate
     - Added "xilinx_srl" for Xilinx shift register extraction
-    - Removed "shregmap -tech xilinx"
+    - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
 
 Yosys 0.8 .. Yosys 0.8-dev
 --------------------------