From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Sep 2021 17:34:16 +0000 (+0100)
Subject: walk whole of sim memory rather than risk missing some addresses
X-Git-Tag: DRAFT_SVP64_0_1~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cee8390ed1b5130e74f67187bf1ec79232f2211c;p=openpower-isa.git

walk whole of sim memory rather than risk missing some addresses
---

diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py
index 4d904e9d..84150a61 100644
--- a/src/openpower/test/state.py
+++ b/src/openpower/test/state.py
@@ -121,10 +121,13 @@ class SimState(State):
     def get_mem(self):
         if False:
             yield
-        keys = list(self.sim.mem.mem.keys())
+        # obtain full list of contents of memory.  assume starts
+        # at address zero.  assumes 64-bit addresses.  use
+        # Mem.ld in order to get data in the correct byteorder
+        simmem = self.sim.mem
         self.mem = []
-        for k in keys:
-            self.mem.append(((k*8), self.sim.mem.mem[k]))
+        for i in range(simmem.depth):
+            self.mem.append((i*8), simmem.ld(i*8, 8, False)))
 
 
 class ExpectedState(State):