From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Nov 2018 11:40:22 +0000 (+0000)
Subject: convert rv_sl to same extra bitwidth arg
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ceee2259ccf747ff9e86c423b5016ebb8d1e3488;p=riscv-isa-sim.git

convert rv_sl to same extra bitwidth arg
---

diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
index 6c52f85..2420481 100644
--- a/riscv/insns/c_slli.h
+++ b/riscv/insns/c_slli.h
@@ -1,3 +1,3 @@
 require_extension('C');
 require(rv_lt(insn.rvc_zimm(), sv_reg_t(xlen)));
-WRITE_RD(sext_xlen(rv_sl(RVC_RS1, insn.rvc_zimm())));
+WRITE_RD(sext_xlen(rv_sl(RVC_RS1, insn.rvc_zimm(), xlen)));