From: Luke Kenneth Casson Leighton Date: Mon, 20 Dec 2021 15:11:46 +0000 (+0000) Subject: more code-comments X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cef77d6d5132fab65bee09feb0d859375632c06c;p=soc.git more code-comments --- diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index 2133c8f1..c70ba8c4 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -122,6 +122,8 @@ class RegStage(RecordObject): # there are 4 quadrants (0-3): here we only support 2 (pt0 and pt3) # these are bits 62-63 of any given address. # except in segment_check, bit 62 is ignored + # Quadrant Select can be seen in v3.0C 6.7.10 p1015 book III figure 36 + # and is further described in 6.7.11.3 p1019 self.pgtbl0 = Signal(64) self.pt0_valid = Signal() self.pgtbl3 = Signal(64)