From: Michel Dänzer <michel.daenzer@amd.com>
Date: Thu, 13 Feb 2014 02:51:09 +0000 (+0900)
Subject: r600g,radeonsi: Consolidate logic for short-circuiting flushes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cf0172d46ab940a691da6516057c81f28961482f;p=mesa.git

r600g,radeonsi: Consolidate logic for short-circuiting flushes

Fixes radeonsi emitting command streams to the kernel even when there
have been no draw calls before a flush, potentially powering up the GPU
needlessly.

Incidentally, this also cuts the runtime of piglit gpu.py in about half
on my Kaveri system, probably because an X11 client going away no longer
always results in a command stream being submitted to the kernel via
glamor.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=65761
Cc: "10.1" mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
---

diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index dc3c22156ff..ef077b21553 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -355,7 +355,7 @@ void r600_begin_new_cs(struct r600_context *ctx)
 	ctx->last_primitive_type = -1;
 	ctx->last_start_instance = -1;
 
-	ctx->initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
+	ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
 }
 
 /* The max number of bytes to copy per packet. */
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 8ea192ac405..0f75a53748f 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -74,7 +74,7 @@ static void r600_flush(struct pipe_context *ctx, unsigned flags)
 	unsigned render_cond_mode = 0;
 	boolean render_cond_cond = FALSE;
 
-	if (rctx->b.rings.gfx.cs->cdw == rctx->initial_gfx_cs_size)
+	if (rctx->b.rings.gfx.cs->cdw == rctx->b.initial_gfx_cs_size)
 		return;
 
 	rctx->b.rings.gfx.flushing = true;
@@ -95,7 +95,7 @@ static void r600_flush(struct pipe_context *ctx, unsigned flags)
 		ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
 	}
 
-	rctx->initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
+	rctx->b.initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
 }
 
 static void r600_flush_from_st(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 15052da8d22..83b0e4f9ce1 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -377,7 +377,6 @@ struct r600_context {
 	struct r600_screen		*screen;
 	struct blitter_context		*blitter;
 	struct u_suballocator		*allocator_fetch_shader;
-	unsigned			initial_gfx_cs_size;
 
 	/* Hardware info. */
 	boolean				has_vertex_cache;
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 068141c347d..e75b3371f59 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -60,7 +60,7 @@ void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 		rusage = RADEON_USAGE_WRITE;
 	}
 
-	if (ctx->rings.gfx.cs->cdw &&
+	if (ctx->rings.gfx.cs->cdw != ctx->initial_gfx_cs_size &&
 	    ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs,
 					     resource->cs_buf, rusage)) {
 		if (usage & PIPE_TRANSFER_DONTBLOCK) {
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 2fbc6a3907a..d604f65226d 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -241,6 +241,7 @@ struct r600_common_context {
 	enum radeon_family		family;
 	enum chip_class			chip_class;
 	struct r600_rings		rings;
+	unsigned			initial_gfx_cs_size;
 
 	struct u_upload_mgr		*uploader;
 	struct u_suballocator		*allocator_so_filled_size;
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index 7e40255a6f2..3437f59d60b 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -81,7 +81,7 @@ void si_context_flush(struct si_context *ctx, unsigned flags)
 {
 	struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
 
-	if (!cs->cdw)
+	if (cs->cdw == ctx->b.initial_gfx_cs_size)
 		return;
 
 	/* suspend queries */
@@ -177,6 +177,8 @@ void si_begin_new_cs(struct si_context *ctx)
 	}
 
 	si_all_descriptors_begin_new_cs(ctx);
+
+	ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw;
 }
 
 #if SI_TRACE_CS